1. Field of the Invention
The present invention relates, in general, to a method for the fabrication of a capacitor in a semiconductor device and, more particularly, to a method capable of augmenting the effective area of a charge storage electrode, thereby affording increased capacitance to the capacitor.
2. Description of the Prior Art
In relation with the integration of dynamic random access memory (hereinafter referred to as "DRAM") in a semiconductor memory device for general use, critical characteristics include the reduction of cell area and the limit in securing enough capacitance according to the reduction. For the purpose of high integration of a semiconductor integrated circuit, the reduction in unit area of the cell results in reduced capacitance. Accordingly, research and development efforts have been directed to securing not only the capacitance but also device reliability.
For a better understanding of the background of the present invention, the description of a conventional method for fabricating a capacitor in a semiconductor device along with its problems is given next, with reference to FIG. 1.
As shown in this figure, over a silicon substrate 1 a field oxide film 2 is formed and then, a field oxide film 3 is formed. The deposition of polysilicon film and the implantation of impurities form a pattern of a gate electrode 4 and a word line 4'.
Thereafter, for the sake of the improvement in electrical properties of a metal oxide semiconductor field effect transistor (hereinafter referred to as "MOSFET"), a MOSFET formation process utilizing spacer oxide films 5 is carried out to form active regions 6,6' having a structure of lightly doped drain (hereinafter referred to as "LDD").
Subsequently, an insulating oxide film 7 with a certain thickness is formed, followed by the formation of a contact hole exposing the active region therethrough. A polysilicon film 11 for charge storage electrode implanted with impurities deposited, coming into contact with the active region through the contact hole. The polysilicon film 11 is patterned on a mask, to form the charge storage electrode.
Over the charge storage electrode, there is covered a composite dielectric film 16, such as nitride-oxide hereinafter referred to as "NO") or oxide-nitride-oxide hereinafter referred to as "ONO") , which, in turn, is covered with a plate electrode 17 which is formed by patterning a polysilicon film implanted with impurities in a predetermined size.
In the light of the capability of present processing, however, the conventional method has difficulty in securing enough charge storage capacitance in a cell as the device is highly integrated. In addition, device reliability becomes deteriorated with the indicated difficulties.